(a) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a protective circuit for protecting the semiconductor device against an electrostatic discharge (ESD)-induced destruction.
(b) Description of the Related Art
A recent increase in integration densities and a recent lowering of operation voltages in integrated circuits generate more various noises on a power supply line (V.sub.cc) and a ground line (GND) resulting in a trend for reduced noise margins.
To avoid erroneous operations resulting from such noises, the V.sub.cc line and the GND line of a VLSI are divided parallel in a layout from a circuit purpose point of view. For instance, to a protective circuit which drains a large amount of current into a ground line, an exclusive ground line is provided separately from a common ground line used for other functional circuits, thereby preventing the functional circuits from operating erroneously by supressing ground bounce phenomena.
Furthermore, an internal circuit expected to exhibit an especially accurate operation such as a sense amplifier is provided with a separate ground line for an exclusive use therefor. Accordingly, semiconductor devices generally have a plurality of separate parallel ground lines.
FIG. 1 is an equivalent circuit diagram of a conventional semiconductor device and its peripheral circuits illustrating therein an input protective circuit 3. The protective circuit 3 clamps the potential of an input terminal 1 to a clamp voltage relative to the potential of a ground line system including first through third ground lines GND1-GND3. In FIG. 1, functional circuits in the semiconductor device, i.e., circuits other than the protective circuit 3 are divided into a first stage circuit 4 for receiving an output from the protective circuit 3 and an internal circuit 5 for receiving an output from the first stage circuit 4. As an example of the first stage circuit 4, a CMOS inverter is illustrated in the drawing.
The first stage circuit 4 functions as an input circuit for the internal circuit 5 in the semiconductor device. As a result of the configuration, the potential of the input terminal 1 is clamped by the input protective circuit 3 when an excessively high voltage is applied to the input terminal 1, so that a surge current flows through a node A and then to a GND terminal 2 via a first ground line GND1. Accordingly, a voltage greater than the clamp voltage is not applied to the first stage circuit 4. Meanwhile, since the parallel ground line system includes the first ground line GND1 for the input protective circuit 3, the second ground line GND2 for the first stage circuit 4 and the third ground line GND3 for the internal circuit 5 separately formed, some interconnection resistances 6 due to their line lengths exist therebetween, whereby propagation of noise is reduced among the circuits 3, 4 and 5.
FIG. 2 is an equivalent circuit diagram showing a second conventional semiconductor device illustrating therein an input protective circuit 3, which clamps an input voltage to a clamp voltage relative to a ground line potential, and its peripheral circuits similarly to the first prior art. Although the input protective circuit 3 operates in a manner similar to that of the semiconductor device of FIG. 1, it provides a problem in its noise-resistive performance because the ground line system is not separated.